Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and reduced power consumption. Metal-oxide-semiconductor (MOS) transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface. Field effect transistors (FETs) are widely used in the electronics industry for amplification, filtering, and other tasks related to both analog and digital electrical signals.
One of the most common FETs is a metal-oxide-semiconductor field effect transistor (MOSFET). MOSFETs generally have a metal or polysilicon gate contact or electrode that is biased to create an electric field in the channel region of a semiconductor body. The semiconductor body can be silicon, strained silicon on SiGe, Ge, or strained silicon by other means. This electric field inverts the channel and enables a current flow between the source region and the drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel region in a semiconductor substrate. The gate dielectric or gate oxide, such as silicon dioxide (SiO2), is normally grown over the channel region, typically by thermal oxidation of the Si substrate. A gate electrode or gate contact is then formed over the gate dielectric, and the gate dielectric and gate electrode materials are then patterned to form a gate structure overlying the channel region of the substrate.
Recent efforts directed to MOS device scaling have accordingly focused on dielectric materials having dielectric constants greater than that of SiO2. These materials, commonly known as high-k dielectric materials, reduce gate current leakage compared to that of equivalent SiO2 or nitrided SiO2 as a result of a higher physical gate dielectric thickness while keeping the overall capacitance density to the required equivalent SiO2 thickness.
Unlike silicon dioxide, high-k gate dielectrics are deposited on the silicon surface rather than grown. Deposition processes usually do not yield surfaces as smooth as those of the grown silicon oxide and the surface roughness of the films can promote device degradation. The relative performance of these high-k materials is often expressed as equivalent oxide thickness (EOT). Equivalent oxide thickness, (teq or EOT) is the thickness of the SiO2 layer (κ˜3.9) having the same capacitance as a given thickness of an alternate dielectric layer.
EOT represents the theoretical thickness of SiO2 that would be required to achieve the same capacitance density as the alternate dielectric and is given by:
      t    eq    =      3.9    ⁢                  ɛ        0            ⁡              (                  A          C                )            
For example, if a SiO2 capacitor is used, and assuming that 1.0 nm of this film produces a capacitance density of (C/A)=34.5 fF/μm2, the physical thickness of an alternate dielectric that must be used in order to achieve the same capacitance density is given by:
            t      eq              κ      ox        =            t              high        -        κ                    κ              high        -        κ            This can be rearranged as:
      t          high      -      κ        =                    κ                  high          -          κ                    3.9        ⁢          t      eq      where 3.9 is κSiO2. Therefore, an alternate gate dielectric with a relative permittivity of 16 and physical thickness of 4.0 nm can be used to obtain teq˜1.0 nm.
Various problems are associated with depositing high-k dielectrics onto substrates; some of these problems are: interfacial SiO2 formation, limited availability of precursors, and very low depositions rates. Furthermore, most of these high-k materials are likely to be crystallized during further thermal processing, creating more defects such as grain boundaries and surface roughness at the dielectric/gate electrode interface. Depositing high-k dielectrics onto substrates also results in a rough surface morphology. Additionally, as the thickness of the gate dielectric material deposited decreases, improvement in surface roughness is required.
Common techniques or methods to deposit high-k dielectrics include chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) processes. The performance and reliability of the resulting transistors with these deposited high-k materials depends upon the bulk quality of the high-k dielectric material, as well as the quality of the interfaces between the high-k gate dielectric material, the gate (which can be poly-silicon or a metal gate), and the channel material. Therefore, there is a need for improved gate structures and fabrication techniques by which high quality gate dielectrics and interfaces can be achieved using high-k dielectric materials.